The present invention relates to a window system synchronizing protective circuit for protecting a synchronizing signal which is detected within detecting windows. More particularly, the present invention relates to a window system synchronizing protective circuit in which the detecting windows are positioned to adjust to the detection synchronizing signal when the detection synchronizing signal has not been detected in the detecting windows for a given period.
A conventional synchronizing protective circuit 1, which is depicted in FIG. 3, serves to monitor a synchronizing signal added to digital data. Circuit 1 also serves to generate a protective synchronizing signal to restrain a signal loss or a fluctuation in signal phase. The detected synchronizing signal triggers a counter 3 for counting bit clock pulses transmitted from a bit clock generating circuit 2. The detected synchronizing signal is also collated with the counting output of the counter 3 by means of a collating circuit 4. The counter 3 outputs a protective synchronizing signal when a numeric value corresponding to a synchronizing period is counted and is simultaneously reset. For this reason, if the phase of the protective synchronizing signal does not match the phase of the detection synchronizing signal, the collating circuit 4 supplies a discordance output to a discordance counter 5. When the number of discordances counted by the discordance counter 5 is in excess of a prescribed number, the detected synchronizing signal is outputted in place of the protective synchronizing signal which has been outputted from the collating circuit 4 up to that time.
The above-described conventional synchronizing protective circuit 1 adopts a so-called resetting method in which the detected synchronizing signal is outputted when there are continuous phasic discordances in excess of a prescribed number between the protective synchronizing signal and the detected synchronizing signal. As illustrated in FIG. 4, once the phase of the detected synchronizing signal fluctuates, it follows that the discordance output signals are consecutively supplied from the discordance counter 5, even if there is no deviation in the synchronizing interval of the subsequent detected synchronizing signals. In the meantime, the output priority is given, not to the detected synchronizing signal, but to the protective synchronizing signal, with the result that this excessive reaction to the disturbance in synchronism further creates a deviation in phase of synchronism. As in the case of a reproduction signal of a compact disc, this synchronizing protective circuit is unsuitable for the synchronizing process of the digital data in which an error rate is low, but the jitter is troublesome.